module _8bits_counter(input clk, input reset, output reg [7:0]out);
reg clk_1;
reg [27:0] temp_1;
always @(posedge clk)
begin
if(temp_1 <= 28'd50000000) begin
if(temp_1 == 28'd50000000) begin
temp_1 <= 28'd0;
clk_1 <= ~clk_1;
end
else begin
temp_1 <= temp_1 + 28'd1;
end
end
else begin
temp_1 <= 28'd0;
end
end
always @(posedge clk_1 or posedge reset)
begin
if(reset)begin
out<=8'd0;
end
else begin
out <=out + 8'd1;
end
end
endmodule
8bits-counter인데 testbench를 못만들어서 오늘 3시간날림..
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